Charge-coupled devices are known to be used as building blocks for digital and analog shift registers. In the prior art an input signal is converted to an amount of charge and the charge is transferred from a charge-coupled device cell to a next charge-coupled device cell, the cells usually being arranged in a row. The last cell in the row is coupled to a charge detector which converts the transferred charge into a suitable output signal. If only two values of charge are being transferred, the device is commonly referred to as a digital shift register and one value of charge is assigned to a logic level 1, the other to a logic level 0, and the cells are referred to as digital charge transfer cells. If all possible amounts of charge within the limitations of the shift register are transferred between cells, the device is referred to as an analog shift register and the cells are referred to as analog charge transfer cells.
The invention is a digital-to analog converter which combines charge-coupled devices in selected combinations for charge-summing and charge-splitting in response to an applied digital signal to implement a digital to analog conversion. The invention selectively divides a reference charge into a plurality of predetermined reference charge portions, selectively sinks or transfers the predetermined reference charge portions to a charge summer in response to an applied digital signal, sums the charge portions and converts the summed charge to produce an analog signal corresponding to the applied digital signal.